Embodiments of present invention relate to memory in general and, in particular, to presetable random access memory.
In electrical circuits, it is common to store data or operating instructions in some type of memory element. In cases where it is desired to allow the user to change this data during circuit operation, the information is typically stored in a Random Access Memory (RAM). A RAM cell, upon reset or startup does not have a predefined usable value. However, particular values may be desired in the RAM upon the RAM receiving a reset signal or a startup signal. Traditionally, designers have sought different approaches to have a RAM cell initialize with a default logic value programmed into the cell, either right after start up or at a selectable point during operation of the circuit, while still offering generic read/write RAM characteristics.
One method to loading RAM with a particular set of values upon power-up or reset is through the use of a ROM (Read Only Memory). While ROMs have been used to load RAM upon reset or startup, relying solely on ROMs may have certain inherent problems. Using ROM takes up physical space on the circuit board it is installed on. Additional circuitry translates to increased cost, power consumption, heat dissipation, and the requirement for the signals from the ROM to be routed to the RAM that is to be programmed using either wires, traces, or vias. Further, a time delay exists between the issuing of the reset/power-up signal to the RAM and ROM, and when the desired values are available to be read from the RAM. This delay is due to the fact the ROM must transfer all desired values to the RAM upon receiving the reset/power-up signal. Relying solely on ROM may result in a significant time delay before the desired values are accessible in the RAM, and may result in less than optimal performance in the implementation of some circuits.
An external ROM is not the only means of setting the values of a RAM. Methods that function internal to RAM cells also exist. An array of SRAM (Static Random Access Memory) cells may be used to store logic values. An array of SRAM cells is made of typically a large number of individual SRAM cells. Upon power-up or reset, the cells of an SRAM array do not have predefined values. FIG. 1 depicts a single SRAM cell. In FIG. 1, a first inverter 105a and a second inverter 105b are cross-connected to form a Latch Loop 110 in a SRAM cell resetting configuration 100. The first inverter 105a and the second inverter 105b each are electrically connected to VDD (VP) and Ground (VG). A Bitline (B) 115a and a Bitline_Bar (BN) 115b electrically connect to a first Latch Loop output (B_INT) 120a and a second Latch Loop output (BN_INT) 120b through a first Bitline Accessing device (MN3) 125a and a second Bitline Accessing device (MN4) 125b respectively. A Wordline (W) 130 is electrically attached to control inputs of the first Bitline Accessing device 125a and the second Bitline Accessing device 125b respectively. Resetting of the SRAM cell occurs by producing a low logic level (Load “0”) and a high logic level (Load “1”) being applied on the Bitline 115a and the Bitline_Bar 115b respectively while a high logic level is applied to the Word line 130. Generally, complementary logic levels applied to the Bitline 115a and the Bitline_Bar 115b, along with application of the assertive logic level (high logic level) on the Word line 130, produce a corresponding logic state in the Latch Loop 110. A method such as this is a problem because it is time-consuming: each cell must be accessed individually using the Bitline, and the wordline.
SRAM is also available in a configuration which has a reset component present within each cell. This embodiment is depicted in FIG. 2. Referring now to FIG. 2, a first inverter 205a and a second inverter 205b are cross-connected to form a Latch Loop 210 in a SRAM cell resetting configuration 200. The first inverter 205a and the second inverter 205b each are electrically connected to VDD (VP) and Ground (VG). A Bitline (B) 215a and a Bitline_Bar (BN) 215b are electrically connected to a first Latch Loop output (B_INT) 220a and a second Latch Loop output (BN_INT) 220b through a first Bitline Accessing device (MN3) 225a and a second Bitline Accessing device (MN4) 225b respectively. A Wordline (W) 230 connects to control inputs of the first Bitline Accessing device 225a and the second Bitline Accessing device 225b respectively. A reset device 235 is connected between an input to the second inverter 205b and Ground. A Reset line (RST) 240 connects to a control input of the Reset device 235. Resetting of the SRAM cell occurs by producing a high logic level on the Reset line 240, which activates the Reset device 235. The active Reset device 235 places a low logic level into the second inverter 205b. The low logic level provided to the input of the second inverter 205b produces reset state for Latch Loop 210. Generally, a reset device may be configured to produce a predetermined logic state in a RAM cell latch loop with corresponding activation. A problem with this method of using a reset device is that each reset device in each SRAM cell is configured identically. Therefore, each reset device sets the same value as each other reset device in other SRAM cells, meaning that upon a reset or power-up signal every cell within the SRAM array is set to the same logical value.
Since different applications may require different default contents of RAM, it is desirable to allow these default contents to be changed inexpensively. However, because of the additional expense of relying solely on ROM and the additional delay for downloading ROM contents into the RAM prior to the contents being accessible in the RAM, it is also desirable to devise a way to incorporate benefits of the programmability and differentiation of ROM with the benefits of a single RAM chip.